Conventional semiconductor devices such as integrated circuits (IC) generally comprise a semiconductor substrate, usually a silicon substrate, and a plurality of conductive material layers separated by insulating material layers. Conductive material layers, or interconnects, form the wiring network of the integrated circuit. Each level of conductor in the wiring network is isolated from the neighboring level of conductors by the insulating layers, also known as interlayer dielectrics. One dielectric material that is commonly used in silicon integrated circuits is silicon dioxide, although there is now a trend to replace at least some of the standard dense silicon dioxide material in IC structures with low-k dielectric materials such as organic, inorganic, spin-on and CVD candidates. Conventionally, IC interconnects are formed by filling a conductor such as copper in features or cavities etched into the dielectric interlayers by a metallization process. Copper is becoming the preferred conductor for interconnect applications because of its low electrical resistance and good electromigration property. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using features such as vias or contacts. In a typical interconnect fabrication process; first an insulating layer is formed on the semiconductor substrate, patterning and etching processes are then performed to form features or cavities such as trenches, vias, and pads etc., in the insulating layer. Then, copper is electroplated to fill all the features. In such electroplating processes, the wafer is placed on a wafer carrier and a cathodic (−) voltage with respect to an electrode is applied to the wafer surface while the electrolyte solution wets both the wafer surface and the electrode.
Once the plating is over, a material removal step such as a chemical mechanical polishing (CMP) process step is conducted to remove the excess copper layer, which is also called copper overburden, from the top surfaces (also called the field region) of the workpiece leaving copper only in the features. An additional material removal step is then employed to remove the other conductive layers such as the barrier/glue layers that are on the field region. Fabrication in this manner results in copper deposits within features that are physically as well as electrically isolated from each other. Other conventional etching techniques can also be used, and conventional approaches exist that can remove both copper and the barrier/glue layers from the field region in one step. A particular type of CMP apparatus that works effectively is described in U.S. Pat. No. 6,103,628 entitled Reverse Linear Polisher with Loadable housing.
The adverse effects of conventional material removal technologies may be minimized or overcome by employing a planar deposition approach that has the ability to provide thin layers of planar conductive material on the workpiece surface, as well as planar removal processes. These planar deposition and removal processes also have application in thru-resist processes employed in IC packaging. In these applications plating is performed into holes opened in resist layers onto seed films exposed on the bottom of each hole or opening.
One technique is collectively referred to as Electrochemical Mechanical Processing (ECMPR), which term is used to include both Electrochemical Mechanical Deposition (ECMD) processes as well as Electro Chemical Mechanical Etching (ECME), and also called Electrochemical Mechanical Polishing. It should be noted that in general both ECMD and ECME processes are referred to as electrochemical mechanical processing (ECMPR) since both involve electrochemical processes and mechanical action.
In one aspect of an ECMPR process, a workpiece surface influencing device (WSID) such as a mask, pad or a sweeper is used during at least a portion of the electrotreatment process when there is physical contact or close proximity and relative motion between the workpiece surface and the WSID. Descriptions of various planar deposition and planar etching methods and apparatus can be found in the following patents and pending applications, all commonly owned by the assignee of the present invention: U.S. Pat. No. 6,176,992, entitled Method and Apparatus for Electrochemical Mechanical Deposition; U.S. application Ser. No. 09/740,701, filed on Dec. 18, 2001, now U.S. Pat. No. 6,534,116, entitled Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence; and U.S. application Ser. No. 09/961,193, filed on September 20, now U.S. Pat. No. 6,921,551, entitled Plating Method and Apparatus for Controlling Deposition on Predetermined Portions of a Workpiece. These methods can deposit metals in and over cavity sections on a workpiece in a planar manner. They also have the capability of yielding novel structures with excess amount of metals over the features irrespective of their size, if desired.
In ECMD methods, the surface of the workpiece is wetted by the electrolyte and is rendered cathodic with respect to an electrode, which is also wetted by the electrolyte. This typically results in conductive material deposition within the features of the workpiece, and a thin layer on the top surface of the workpiece. During ECMD, the wafer surface is pushed against or in close proximity to the surface of the WSID or vice versa when relative motion between the surface of the workpiece and the WSID results in sweeping of the workpiece surface. Planar deposition is achieved due to this sweeping action as described in the above-cited patent applications.
In ECME methods, the surface of the workpiece is wetted by the electrolyte or etching solution, but the polarity of the applied voltage is reversed, thus rendering the workpiece surface more anodic compared to the electrode. If no voltage difference is applied, the etching is chemical etching and can be performed when there is physical contact or close proximity between the workpiece and the WSID. The chemical etching can be carried out using the process solution or an etching solution.
Very thin planar deposits can be obtained by first depositing a planar layer using an ECMD technique and then using an ECME technique on the planar film in the same electrolyte by reversing the applied voltage. Alternately the ECME step can be carried out in a separate machine and a different etching electrolyte. The thickness of the deposit may be reduced in a planar manner. In fact, an ECME technique may be continued until all the metal on the field regions is removed. It should be noted that a WSID may or may not be used during the electroetching or etching process since substantially planar etching can be achieved with or without the use of WSID.
FIG. 1A, is a schematic illustration of an exemplary conventional ECMPR system 100 used for processing wafers. In FIG. 1A, a WSID 102 having openings 104 in it, is disposed in close proximity of a workpiece or wafer 106 to be processed. The WSID 102 is supported by a support plate 108 having perforations 110 or openings in it. The wafer 106 is a silicon wafer to be plated with a conductive material, preferably copper or a copper alloy. The wafer 106 is retained by a wafer carrier 111 so as to position front surface 112 of the wafer against top surface 113 of the WSID 102. The openings 104 are designed to assure uniform deposition of copper from an electrolyte solution, depicted by arrows 114, onto the front surface 112, or uniform electroetching from the front surface 112. The perforations 110 may or may not exactly match the design of the openings 104. Generally, the openings 104 are designed for uniform deposition, and perforations 110 are such that the electrical field and electrolyte solution pass substantially unhindered to the WSID 102. Therefore, the area of perforations per unit area of the support plate 108 is equal to or larger than the area of the openings per unit area of the WSID 102. The top surface 113 of the WSID 102 facing the front surface 112 of the wafer is used as the sweeper and the WSID 102 itself establishes appropriate electrolyte flow and electric field flow to the front surface 112 for globally uniform deposition or etching. Such an ECMPR system 100 also includes an electrode 116, which is immersed in the electrolyte solution 114. The electrolyte 114 is in fluid communication with the electrode 116 and the front surface 112 of the wafer 106 through the openings 104 in the WSID 102.
The electrode 116 is typically a Cu piece for Cu deposition. It may also be an inert electrode made of, for example, Pt coated Ti. An exemplary copper electrolyte solution may be copper sulfate solution with additives such as accelerators, suppressors, leveler, chloride and such, which are commonly used in the industry. In planar deposition techniques such as ECMD, the leveler is not very necessary since leveling is automatically done by the process. Leveler may be added however, for optimization of other process results such as gap fill, etc. The top surface 113 of the WSID 102 sweeps the front surface 112 of the wafer 106 while an electrical potential is established between the electrode 116 and the front surface 112 of the wafer 106. For deposition of a planar film such as copper, the front surface 112 of the wafer 106 is made more cathodic (negative) compared to the electrode 116, which becomes the anode. For electroetching in the same ECMPR system, the wafer surface 112 is made more anodic than the electrode 116. For chemical etching or etching, no potential difference is applied between the wafer 106 and the electrode 116.
As shown in FIG. 1B, the structure of the WSID 102 may have a top layer 120, an intermediate layer 122, and a bottom layer 124. The top layer 120 may preferably be made of an abrasive material such as a the class of fixed-abrasive-films supplied by the 3M company, or any of the other so-called pad materials used in CMP applications, such as the polymeric IC-1000 material supplied by Rodel. The thickness of the top layer 120 may be typically in the range of 0.05-2 mm. The intermediate layer 122 is the mounting layer for the top layer 120 and the holes are defined in the intermediate layer 122 and the bottom layer 124. The intermediate layer 122 is typically made of a hard plastic material such as polycarbonate with a thickness range of 1-3 mm. The bottom layer 124 functions as a compression layer for the whole structure. The bottom layer is made of a polymeric foam material such as polyurethane or polypropylene. U.S. Pat. Nos. 6,413,403 and 6,413,388, which are assigned to the assignee of the present invention, disclose various examples of WSIDs. Further, U.S. patent application Ser. No. 09/960,236% filed on Sep. 20, 2001, now U.S. Pat. No. 7,201,829, entitled Mask Plate Design, discloses various WSID embodiments. Further, U.S. patent application Ser. No. 10/155,828, filed on May 23, 2002, now U.S. Pat. No. 7,238,092, entitled Low Force Electrochemical Mechanical Deposition Method and Apparatus, discloses a WSID structure having a flexible and abrasive top layer attached on a highly compressible layer. Both patents are assigned to the assignee of the present invention. The WSID is placed on a porous support plate which may be or may not be an integral part of the WSID. In this particular structure, electrolyte is flowed through the openings or the open pores of the compressible layer and the openings in the flexible layer.
To this end, however, while these techniques assist in obtaining planar metal deposits or novel metal structures on workpieces and wafers, there is still a need for further development of high-throughput approaches and devices that can yield deposits with better uniformity and high yield.